upgrade from Altium 2004 to Altium 6.3

Last night I upgraded from DXP2004 to 6.3. I tried to start working on the FPGA design part - when 2004 announced (with profound dignity) it will not support my ambitious attempt to use a Xilinx Spartan-3 "3rd party" board. Turned out its just the XCS400 core that DXP 2004 doesnt support - so i decided to upgrade to 6.3 after an hour of googling and altiuming (if u can call browsing their website so). The upgrade process took the better part of another hour. And afterwards I found out 6.3 supports spartan-3 3rd party boards - only if you have the xilinx ISE installed. That is precisely when I lost what ever modicum of patience i still had and left it hanging thr. I came back to work in the afternoon and soon found out (i) one of my eight schematics shows an empty sheet when i open it in 6.3; (ii) 6.3 cant find the footprints of the caps, the resistors, the diodes and most of my IC's (the ones i used from 2004 libraries). So I diligently strted re-doing them all. Redid the schematic and by 6 in the morning everything was as it used to be. Except for the FPGA which in stead of having one very large part and one small part has 9 small parts now.

I decided to stop wallowing(!) in my sorrow of my supervisor being incommunicado and AWOL somewhere in england. I will continue following the normal design-flow - which means the next task is starting on a PCB design. The schematics are almost completed - except for

Footprint re-check
Schematic re-checking by a qualified engineer (meaning a teacher)
I/Q summing
line driver circuitry
JTAG chain
z8 interfacing to s3

I was thinking of routing all remaining z8 GPIO's to the s3. That way i wont have to worry about the format of the information that will pass between the two right now. I know I almost certainly have enough I/O's to have parellel comm - but if need be old serial comm is still there. And comm between the two will be asynchronous and initiated by user inputs in anycase. A parellel interface may not be that necessary.

I would like to start on the FPGA part of the design concurrently - which means I have to get my hands on the Xilinx ISE (1.5GB). That with a 55kbps DSL.

Last night I figured out how to interface my digilent s3 board to altium. I still need xilinx ise to synthesize the hdl codes.